Test equipment is typically used to determine whether a device under test ("DUT") follows a set of timing and drive strength specifications. Accordingly, testing accuracy plays a vital role in the design of test equipment because a discrepancy in measurements can result in an incorrect classification of a DUT. For example, in some testing environments, provided a DUT follows a set of predetermined specifications, the DUT is categorized as a valid device for sale. Typically, to pass as a valid device each pin of a given DUT must satisfy both timing and drive strength requirements. Typical timing requirements include valid time, hold time, and setup time. Typical drive strength requirements include driving an output to a predetermined voltage despite an opposing current source load.
Prior art testers use a diode bridge system to determine the drive strength of a DUT output. The diode bridge allows a tester to determine the high-state drive capability of a DUT by sinking current out of the DUT when the DUT is driving an output pin to a high voltage. Alternatively, the diode bridge allows a tester to determine the low-state drive capability of a DUT by sourcing current into the DUT when the DUT is driving an output pin to a low voltage.
FIG. 1 illustrates a prior art testing system. In particular, test system 100 is used to determine the drive strength of a DUT pin coupled to output Vd 130. To test the drive strength of the DUT pin, system 100 compares the voltage on input voltage switch ("Vs") 110 to the voltage on output Vd 130 via the diode bridge consisting of Schottky diodes D1, D2, D3, and D4--the diodes are typically forward biased during a 0.5 voltage drop. If the voltage on Vd 130 is greater than the voltage on Vs 110, system 100 sinks current away from the DUT via current source ("Is") 125. Thus, testing the drive strength of the DUT when the DUT is driving an output pin to a high voltage. On the other hand, if the voltage on Vd 130 is less than the voltage on Vs 110, system 100 injects current into the DUT via current source ("Is") 120. Thus, testing the drive strength of the DUT when the DUT is driving an output pin to a low voltage.
During the testing of a DUT pin coupled to output Vd 130, system 100 sets Vs 110 to the switch point voltage of the DUT and closes both switches S121 and S126. As illustrated in FIG. 1, Vs 110 is coupled to buffer 115 which, in turn, is coupled to an intermediate node (N112) of the diode bridge. Typically, buffer 115 is a unity buffer that transfers the voltage on Vs 110 to node N112. Thus, Vs 110 is compared to Vd 130 via the intermediate nodes of the diode bridge. In particular, as the voltage on Vd 130 increases past Vs 110, diodes D4 and D1 are forward biased while diodes D3 and D1 are reverse biased. Thus, Is 125 sinks current out of Vd 130. Alternatively, as the voltage on Vd 130 decreases below Vs 110, diodes D3 and D2 are forward biased while diodes D4 and D1 are reverse biased. Thus, Is 120 injects current into Vd 130.
System 100 allows prior art testers to accurately test the drive strength of slow speed devices. Prior art testers, however, create numerous disadvantages during the testing of high speed or low power devices. For example, one disadvantage of system 100 is evident during the testing of low power devices. In particular, during power measurements of a low power DUT coupled to node Vd 130, the leakage in the Schottky diodes (D1-D4) results in a data offset of the power supply current measurement. Thus, system 100 incorrectly classifies low power devices as having a high direct current ("DC") leakage.
Another disadvantage of prior art testers results form the inconsistent loading characteristics of system 100. Specifically, if Vd 130 is coupled to an input/output ("I/O") pin of a DUT, system 100 operates in two different modes. If the I/O pin is operating as an input, system 100 switches S121 and S126 to an off position. If the I/O pin is operating as an output, however, system 100 switches S121 and S126 to an on position. The transition between the two modes results in nodes N113 and N111 floating to an undetermined value, thus resulting in a timing error during the testing of high speed devices.
For example, Vd 130 is coupled to an I/O pin of a DUT with a 0 to 5 voltage swing. System 100 sets Vs to 2.5 volts. As previously described, during the input testing of the DUT, system 100 moves switches S121 and S126 to an off position. Thus, resulting in node N113 floating to a voltage value between 2 and 5 volts. Subsequently, during the drive strength testing of node Vd 130, system 100 moves switches S121 and S126 to an on position. During the initial low-to-high transition of the DUT output, D4 turns on and the capacitive loading of node N113 is transferred to node Vd 130. However, on a subsequent low-to-high transition of the DUT output, D4 remains off because node N113 was previously driven to a high stage, thus the capacitive loading of node N113 is not transferred to node Vd 130. The inconsistent transfer of capacitive loading results in a timing error.
FIG. 1 also illustrates the timing errors created by the inconsistent transfer of capacitive loading by system 100. In particular chart 105 outlines the voltage transitions of output Vd 130 during the two different modes of system 100. The horizontal axis of timing chart 105 shows time ("t"). The vertical axis of timing chart 015 shows the voltage level on output Vd 130.
Prior to time period 106, the DUT pin coupled to output Vd 130 is used as an input. Accordingly, system 100 moves switches S121 and S126 to the off position. Subsequently, system 100 is used to determine the drive strength of the DUT pin coupled to Vd 130. Accordingly, system 100 moves switches S121 and S126 to the off position. As previously described, the initial low-to-high transition of output Vd 130 incurs additional capacitive loading. Thus, as illustrated in timing chart 105, voltage rise time 150 is slower than voltage rise time 155. In prior art slow speed devices the difference in rise times is considered negligible. In high speed devices, however, the tester generated difference in rise time may lead to an incorrect characterization of a high speed device as an invalid device.
Yet another disadvantage of prior art testers results from using system 100 as a low voltage driver. FIG. 2 illustrates a prior art low voltage driver used to drive wave forms on a DUT input coupled to output Vd 230. System 200 includes input Vtest 255 coupled to driver 220 which, in turn, is coupled to resistor (R215). R215 is also coupled to load 210 (corresponding to system 100) and output VD 230. Typically, driver 220 is a unity buffer that transfers the value on input Vtest 255 to node N211. System 200 creates voltage swings on output Vd 230 by controlling the values of input Vtest 225, R215, and the switching times of S121 and S126.
For example, to generate a low voltage output on a DUT input. System 200 sets Vtest 225 to 50 milli-volts ("mV"), R 215 to 50 ohms, and VS 110 to -2 volts--thus ensuring that system 100 only performs a current sink. System 200 also sets both Is 120 and Is 125 to 2 milli-amperes ("mA"). As system 200, moves switches S121 and S126 between the on and off position, either 2 mA of current is sunk out off Vd 230 or Vd 230 is left floating. Thus, resulting in an output on VD 230 that transitions between -0.05 volts an 0.05 volts.
As previously described, the switching of S121 and S126 creates inconsistent transfer of capacitive loading by system 100. The low voltage driver of system 200, however, requires the switching of S121 and S126 to create a wave form on output Vd 130. Accordingly, the inconsistent transfer of capacitive loading by system 100 results in inconsistent wave forms on output Vd 230. Furthermore, system 100 creates an over shoot of sunk current. Thus, creating further inconsistencies in the wave forms generated on output Vd 230. In prior art testing of slow speed devices, the inconsistent wave forms generated on output Vd 230 are considered negligible. In high speed devices, however, the inconsistent wave forms generated on output Vd 230 may lead to an incorrect characterization of a high speed device as an invalid device.